This invention relates to determining dependency between instructions to be executed. In particular, the invention relates to methods and apparatus for determining register dependency in multiple architecture systems.
Microprocessors exist that can implement multiple instruction sets by emulating one instruction set with another. One example is using a reduced instruction set computing (RISC) instruction set architecture (ISA) to implement an independent complex instruction set computing (CISC) ISA by emulating the CISC instruction with instructions native to the RISC instruction set. Instructions from the CISC ISA are called xe2x80x9cmacroinstructions.xe2x80x9d Instructions from a RISC ISA are called xe2x80x9cmicroinstructions.xe2x80x9d Existing microprocessors do not implement these two architectures as efficiently as can be done.
To improve performance, it is desirable to execute multiple microinstructions in each clock cycle. A macroinstructions that is emulated by one or more microinstructions is called a xe2x80x9cflowxe2x80x9d. The flows for the emulated instruction set are contained in a ROM called xe2x80x9cmicrocode.xe2x80x9d Microcode, used to provide a sequence of microinstructions to emulate a given macroinstruction, cannot statically determine dependencies between a sequence of microinstructions that emulates a single macroinstruction, nor between a sequence of microinstructions that are used to emulate a sequence of macroinstructions. The primary reason behind this is due to register aliasing. Aliasing is a term that refers to filling in various parts of the microcode instruction with information directly from the macroinstruction, allowing different macroinstructions to be combined in the microcode. In order to allow two instructions from these two cases to be executed together, there is a need for some sort of hardware to do dependency checking.
One example of a CISC ISA is the IA-32 instruction set (also know as the xc3x9786 instruction set). IA-32 defines eight integer registers and eight floating point registers. In IA-32 computer systems, the floating point unit (FPU) comprises a plurality of data registers. Floating point instructions treat this plurality of data registers as a register stack. All addressing of the data registers is relative to the register on the top of the stack. The register number of the current top-of-stack register is stored in a stack TOS field. Thus, load operations decrement TOS by one and load a value in to the new top-of-stack register, which store operations, store the value from the current top-of-stack register in memory and then increment TOS by one. Most floating point instructions use this register stack.
In addition to the floating point top-of-stack pointer, the FPU architecture defines a floating point tag word (FPTW). The FPTW indicates whether a stack register is empty or not. An exception occurs when an operation attempts to read the contents of an empty stack register (known as xe2x80x9cstack underflowxe2x80x9d) or tries to overwrite the contents of a full stack register (known as xe2x80x9cstack overflowxe2x80x9d). In order to properly emulate the IA-32 instruction set, both of these architectural features must be emulated.
More information regarding the FPU architecture can be found in the Intel Architecture Software Developer""s Manual, Volumes 1-3, which are hereby incorporated by reference.
A method consistent with the present invention to determine register dependency. The method includes providing native instructions, where one or more of the native instructions emulate an emulated instruction and the native instruction contains at least one register identifier. In addition, providing at least one flag for each native instruction where each flags indicates whether one of the at least one register identifier is valid. Finally, checking for dependencies among the valid register identifiers in the native instruction.
An apparatus consistent with the present invention determines register dependency. The apparatus includes a microprocessor to emulate an emulated instruction set using a native instruction set, where the microprocessor includes at least one register. An execution engine to provide one or more native instructions where each native instruction contains at least one register identifier. One or more flags are provided to each native instruction where each of the flags indicate whether the register identifier is valid. A bundler to check for dependency among the valid identifiers in the native instructions.